1. Field of the Invention
This invention relates to a hierarchical differential sensing approach and in particular to an array of 1T DRAM cells are organized in rows and columns in which the rows represent words and the columns represent bits of the word, each bit column having more than one pair of balanced, true and complement local bit lines, the local bit lines being connected to a pair of balanced, true and complement global bit lines by way of CMOS transistor switches.
2. Description of Background
Random access memories (RAMs) are well known in the art. A typical RAM has a memory array wherein every location is addressable and freely accessible by providing the correct corresponding address. Dynamic RAMs (DRAMs) are dense RAMs with a very small memory cell. High performance Static RAMs (SRAMs) are somewhat less dense (and generally more expensive per bit) than DRAMs, but expend more power in each access to achieve speed, i.e., provide better access times than DRAMs at the cost of higher power. In a typical data processing system, the bulk of the memory is DRAM in main memory with faster SRAM in cache memory, closer to the processor or microprocessor. Caching is an effective technique for increasing microprocessor performance. RAMs are commonly made in the well-known complementary insulated gate field effect transistor (FET) technology known as CMOS.
A typical CMOS logic circuit, for example, includes paired complementary devices, i.e., an n-type FET (NFET) paired with a corresponding p-type FET (PFET), usually gated by the same signal. Since the pair of devices have operating characteristics that are, essentially, opposite each other, when one device (e.g., the NFET) is ‘ON’ and conducting (ideally modeled as a resistor (R) in series with the closed switch), the other device (the PFET) is ‘OFF’, not conducting (ideally modeled as an open switch) and, vice versa. For example, a CMOS inverter is a series connected PFET and NFET pair that are connected between a power supply voltage (Vdd) and ground (GND). A typical static random access memory (SRAM) cell ideally includes a balanced pair of cross-coupled inverters storing a single data bit with a high at the output of one inverter and a low at the output of the other. A pair of pass gates (also ideally, a balanced pair of FETs) selectively connects the complementary outputs of the cross-coupled inverter to a corresponding complementary pair of bit lines. A word line connected to the gates of the pass gate FETs selects connecting the cell to the corresponding complementary pair of bit lines. During a cell access, the pass gates are turned ‘ON’ to couple the bit line contents to the cross-coupled inverters. In a well designed SRAM, once data is stored in a cell and unless power is lost, the cell maintains that data until it is overwritten.
A DRAM cell is essentially a capacitor for storing charge and a switch, a pass transistor (also called a pass gate or access transistor) that switches ‘ON’ and ‘OFF’ to transfer charge to and from the capacitor. Thus, a typical DRAM cell is much smaller (denser) than a typical SRAM cell, e.g., <¼. Data (1 bit) stored in the cell is determined by the absence or presence of charge on the storage capacitor. Since each cell has numerous leakage paths from the storage capacitor, unless it is periodically refreshed, charge stored on the storage capacitor eventually leaks off, Each DRAM cell is read by coupling the cell's storage capacitor (through the access transistor) to a bit line, which is a larger capacitance, and measuring the resulting voltage difference on the bit line. Since each time a cell is read, the voltage on the storage capacitor is equalized with the voltage on the bit line, the cell's contents are destroyed by the read, i.e., a destructive read.
As is further well known in the art, the maximum voltage that an FET pass gate will pass is its gate to source voltage (Vgs) reduced by the FET turn-on or threshold voltage (VT), i.e., the stored voltage (VSt) on the storage capacitor (Ccell) is VSt=Vgs−VT. The magnitude of the signal (Vsig) transferred to the bit line with capacitance CBL is VSig=CcellVSt/(Ccell+CBL), In a typical state of the art DRAM (e.g., 256 Mbit or 1 Gbit) with up to 512 or even 1024 bits on each bit line, CBL is at least one order of magnitude larger than Ccell. So, Vsig is typically at least an order of magnitude smaller than the supply voltage, Vdd, and is, typically, a few hundred millivolts (mv). Further, that signal develops exponentially with a time constant dependent upon the overall RC time constant of the signal path, i.e., where ‘R’ includes the FET on resistance and C=Ccell+CBL. Thus, developing a sufficient bit line signal to sense, i.e. to transfer a portion of VSt to the bit line, typically accounts for most of the read time of a state of the art DRAM.
Unfortunately, DRAM read time has been much longer than SRAM read time, e.g., an order of magnitude. Consequently, this longer read time has been a significant deterrent to using DRAM in high performance logic chips and the primary reason less dense but faster SRAM is used for cache memory.
Thus, there is a need for high performance DRAMs, especially with reduced cell read times and more particularly, for high performance DRAMs suitable for embedded use in logic chips.